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TDA7311 serial bus controlled audio processor input multiplexer C two stereo differential inputs C two stereo single ended inputs C one mono differential input input and output for external equalizer or noise reduction sys- tem volume control in 1.25db steps treble and bass control four speaker attenuators: C 4 independent speakers control in 1.25db steps for balance and fader facilities C independent mute function all functions programmable via spi compatible serial bus description the TDA7311 is a volume, tone (bass and treble) and fader (front/rear) processor for high quality audio applications in car radio and hi-fi systems. control is accomplished by serial bus microproc- essor interface. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are ob- tained. july 1999 pins connection (top view) ordering number: TDA7311 dip40 ? 1/11
test circuit thermal data symbol description dip40 unit r th j-pins thermal resistance junction-pins max 85 c/w quick reference data symbol parameter min. typ. max. unit v s supply voltage 8 10 11 v v cl max. input signal handling 2.3 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 % s/n signal to noise ratio 106 db s c channel separation f = 1khz 95 db volume control 1.25db step -78.75 +11.25 db treble control 2db step -14 +14 db br ss bass control 2db step C20 +20 db fader and balance control 1.25db step -38.75 0 db mute attenuation 92 db absolute maximum ratings symbol parameter value unit v s operating supply voltage 11.2 v t op operating temperature range -40 to 85 c t stg storage temperature range -55 to +150 c TDA7311 2/11
9 8 4 5 in4 in3 diff stereo 1 left inputs supply secmute 34 35 right inputs 1 40 2 v cc an-gnd cref 10 11 vol bass 12 13 treble 14 mute d94au178 mute spi bus decoder + latches spkr att spkr att 15 16 vol bass treble 31 30 29 28 mute spkr att mute spkr att 20 19 18 21 26 25 cl da ce dig gnd out right front out right rear out left rear out left front 27 7 6 diff stereo 2 38 3 diff mono secmute 37 36 33 32 diff stereo 2 diff stereo 1 in3 in4 block diagram TDA7311 3/11
electrical characteristics (t amb = 25c, v cc = 10v, r l = 10k w , r g = 600 w , g v =0db, f = 1khz unless otherwise specified) (refer to the test circuit) symbol parameter test condition min. typ. max. unit supply v s supply voltage 8 10 11 v i s supply current 15 20 ma svr ripple rejection 55 80 db input selectors r ii input resistance single ended inputs 30 50 70 k w differential inputs 10 20 k w v cl clipping level single ended inputs 2.3 2.8 vrms differential inputs 4.6 5.6 vrms cmrr common mode rejection differential inputs 65 db ins input separation (2) 70 90 db r l output load resistance 2 k w c l output load capacitance 1 nf r o output impedance 15 50 w g in input gain single ended inputs -1 0 1 db differential inputs -7 -6 -5 db volume control r in input resistance 15 30 k w g r control range max. attenuation C 75 db max. gain +11.25 db a step step resolution 1.25 db e a attenuation set error a v = +11.25 to -20db a v = -20 to -60db -1.25 -3 0 1.25 2 db db e t tracking error 2db v dc dc steps adjacent attenuation steps from 0db to a vmax 0 1 3.0 10.0 mv mv vimax. max. input voltage 2.3 2.8 vrms speaker attenuators a r control range 37.5 db a step step resolution 1.25 db e a attenuation set error 1.5 db v dc dc steps adjacent att. steps from 0 to mute 0 1 mv mv bass control (1) control range +20 db step resolution 2 db attenuation / gain set error C2.0 2.0 db treble control (1) control range +14 db step resolution 2.0 db attenuation / gain set error C1.0 0 1.0 db TDA7311 4/11
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit audio outputs output voltage d = 0.3% 2.3 2.8 vrms output load resistance 2 k w output load capacitance 10 nf output resistance 25 75 w dc voltage level 4.6 5.0 5.4 v general e no output noise bw = 20-20khz, flat output muted all gains = 0db single ended all gains = 0db diff. inputs 4 5 10 15 30 m v m v m v s/n signal to noise ratio all gains = 0db; v o = 1vrms single ended differential inputs 106 100 db db d distortion v in = 1vrms 0.01 % sc channel separation left/right 70 95 db total tracking error a v = 0 to -20db a v = -20 to -60 db a v = 0db to 11.25db 0 0 0 1 2 1 db db db output attenuation mute condition (3) 80 90 db bus inputs v il input low voltage 1 v v ih input high voltage 3 v notes: (1) bass and treble response see attached diagram (fig.17). the center frequency and quality of the resonance behaviour can be choosen by the external circuitry. a standard first order bass response can be realized by a standard feedback network (2) the selected input is grounded thru the 2.2 m f capacitor. (3) condition obtained programming: mute on speaker attenuators (1x111111) followed by selection of secmute (1xxxx111). TDA7311 5/11
application information serial bus interface the serial bus interface is compatible to spi bus systems. during the low state of the chip enable signal (ce) the data on pin da are clocked into the shift register at the low to high transition of the clock signal cl. at the low to high transition of the ce signal the content of the internal shift register is stored into the addressed latches. the transmission is separated into bytes with 8 bit according to the data specification of the audio- processor. after every byte a positive slope of the ce signal has to be generated in order to store the data byte. a special clock counter enables the latch of the data byte only, if exactly 8 clocks were present during the low state of the ce signal. this re- sults in a high immunity against spikes on the clock line and avoids a storage of wrong databy- tes. figure 1: bus timing nr. parameter min. max. units clock frequency 250 khz 1 ce lead time 4 m s 2 clock high time 2 m s 3 clock low time 2 m s 4 data hold time 1.8 m s 5 data setup time 1.8 m s 6 clock setup time 0 m s 7 ce lagtime 0 m s 8 clock hold time 6 m s 9 ce high time 6 m s TDA7311 6/11
second byte volume attenuation msb lsb 1 x b2 b1 b0 a2 a1 a0 volume 1.25db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5.00 -6.25 -7.50 -8.75 1 x b2 b1 b0 volume 10db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -10 -20 -30 -40 -50 -60 -70 software specification data bytes first byte msb lsb function 0000xxxxvol attenuation 0100xxxxvol gain 0010xxxx bass 0110xxxx treble 0001xxxx att rf (speaker) 0101xxxx att rr (speaker) 0011xxxx att lf (speaker) 01110xxx att lr (speaker) 01111xxx audio switch status after power-on reset volume C78.75db speaker mute audio switch mute bass C20db treble C14db TDA7311 7/11
software specification (continued) volume gain msb lsb 1.25db steps 1 x x x 0 0 0 0 0.00 1 x x x 0 0 0 1 1.25 1 x x x 0 0 1 0 2.50 1 x x x 0 0 1 1 3.75 1 x x x 0 1 0 0 5.00 1 x x x 0 1 0 1 6.25 1 x x x 0 1 1 0 7.50 1 x x x 0 1 1 1 8.75 1xxx10 0 0 10.00 1xxx10 0 1 11.25 speaker attenuation msb lsb 1.25db steps 1 000 0 1 001 -1.25 1 010 -2.50 1 011 -3.75 1 100 -5.00 1 101 -6.25 1 110 -7.50 1 111 -8.75 10db steps 1x000 0 1x001 -10 1x010 -20 1x011 -30 1x111111 mute audio switch msb lsb input 1xxxx0 0 0 mono 1xxxx0 0 1 diff1 1xxxx0 1 0 diff2 1xxxx0 1 1in3 1xxxx1 0 0in4 1xxxx1 1 1 secmute TDA7311 8/11
software specification (continued) treble msb lsb 2db steps 1xxx01 1 1 14 1xxx01 1 0 12 1xxx01 0 1 10 1xxx01 0 0 8 1xxx00 1 1 6 1xxx00 1 0 4 1xxx00 0 1 2 1xxx00 0 0 0 1xxx10 0 0 -0 1xxx10 0 1 -2 1xxx10 1 0 -4 1xxx10 1 1 -6 1xxx11 0 0 -8 1xxx11 0 1 -10 1xxx11 1 0 -12 1xxx11 1 1 -14 bass msb lsb 2db steps 1xx11111 -20 1xx11001 -18 1xx11000 -16 1xx10111 -14 1xx10110 -12 1xx10101 -10 1xx10100 -8 1xx10011 -6 1xx10010 -4 1xx10001 -2 1xx10000 0 1xx00000 0 1xx00001 2 1xx00010 4 1xx00011 6 1xx00100 8 1xx00101 10 1xx00110 12 1xx00111 14 1xx01000 16 1xx01001 18 1xx01111 20 TDA7311 9/11
dim. mm inch min typ max min typ max a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 52.58 2.070 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip40 outline and mechanical data TDA7311 10/11
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com TDA7311 11/11

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